In the fabrication of prototype integrated circuits, particularly gate arrays of the double metal layer C-MOS type, prepared wafers are prepared using conventional mass production techniques. The upper four layers of the prototype integrated circuits are left to be specifically configured to a particular application. These layers include a contact layer having apertures through which contact is established with semiconductors disposed therebelow, a metal I layer disposed over the contact layer, an insulation layer, termed a via layer, having apertures through which contact is established with the metal I layer, and a metal II layer, which is the upper metal layer of the integrated circuit.
Normally a passivation layer, such as SiO.sub.2, is provided over the metal II layer for mechanical protection as well as electrical insulation of the integrated circuit.
Upon definition of a specific application for a prototype integrated circuit, the following steps are carried out:
The contact layer is covered with photoresist.
A specific mask formed for a given application for contact layer configuration is used to expose the photoresist overlying the contact layer in order to expose all of the required contacts which define electrical connections with underlying semiconductor devices.
The unwanted regions of photoresist are removed.
The portions of the contact layer underlying the regions at which photoresist has been removed are etched.
The remaining photoresist is removed.
The contact layer may be pre-configured and thus the above steps may form part of the mass production phase and not part of the specific configuration for specific applications.
After configuration of the contact layer, the metal I layer is deposited and the following steps are carried out:
The metal I layer is covered with photoresist.
A specific mask formed for a given application for metal I configuration is used to expose the photoresist overlying the metal I layer in order to form all of the required metal I lines which define electrical connections with underlying semiconductor devices.
The unwanted regions of photoresist are removed.
The portions of the metal I layer underlying the regions at which photoresist has been removed are etched.
The remaining photoresist is removed.
After configuration of the metal I layer, the via layer is deposited and the following steps are carried out:
The via layer is covered with photoresist.
A specific mask formed for a given application for via configuration is used to expose the photoresist overlying the via layer in order to expose all of the required contacts which define electrical connections with the underlying metal I layer.
The unwanted regions of photoresist are removed.
The portions of the via layer underlying the regions at which photoresist has been removed are etched.
The remaining photoresist is removed.
After configuration of the via layer, the metal II layer is deposited and the following steps are carried out:
The metal II layer is covered with photoresist.
A specific mask formed for a given application for metal II configuration is used to expose the photoresist overlying the metal II layer in order to form all of the required interconnects which define electrical connections with the underlying metal I lines.
The unwanted regions of photoresist are removed.
The portions of the metal II layer underlying the regions at which photoresist has been removed are etched.
The remaining photoresist is removed.
Following configuration of the metal II layer, the passivation layer is deposited and then typically configured using a general purpose mask in order to define windows in the passivation layer for circuit pads to which leads are connected, for electrical connections to the integrated circuit.